/*
 * Copyright : (C) 2024 Termony Technology, Inc. All Rights Reserved.
 */

#ifndef RK_VCCIO3_5_IOC_HW_H
#define RK_VCCIO3_5_IOC_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

/** @name Register Map
 *
 * Register offsets for the VCCIO3_5_IOC.
 */
#define RK_VCCIO3_5_IOC_GPIO2A_DS_H_OFFSET          0x0044U /* GPIO2A Driver Strength Control High bits */
#define RK_VCCIO3_5_IOC_GPIO2B_DS_L_OFFSET          0x0048U /* GPIO2B Driver Strength Control Low bits */
#define RK_VCCIO3_5_IOC_GPIO2B_DS_L_OFFSET          0x004CU /* GPIO2B Driver Strength Control high bits */
#define RK_VCCIO3_5_IOC_GPIO2C_DS_L_OFFSET          0x0050U /* GPIO2C Driver Strength Control Low bits */
#define RK_VCCIO3_5_IOC_GPIO2C_DS_H_OFFSET          0x0054U /* GPIO2C Driver Strength Control High bits */
#define RK_VCCIO3_5_IOC_GPIO3A_DS_L_OFFSET          0x0060U /* GPIO3A Driver Strength Control Low bits */
#define RK_VCCIO3_5_IOC_GPIO3A_DS_L_OFFSET          0x0064U /* GPIO3A Driver Strength Control high bits */
#define RK_VCCIO3_5_IOC_GPIO3B_DS_L_OFFSET          0x0068U /* GPIO3B Driver Strength Control Low bits */
#define RK_VCCIO3_5_IOC_GPIO3B_DS_L_OFFSET          0x006CU /* GPIO3B Driver Strength Control high bits */
#define RK_VCCIO3_5_IOC_GPIO3C_DS_L_OFFSET          0x0070U /* GPIO3C Driver Strength Control Low bits */
#define RK_VCCIO3_5_IOC_GPIO3C_DS_L_OFFSET          0x0074U /* GPIO3C Driver Strength Control high bits */
#define RK_VCCIO3_5_IOC_GPIO3D_DS_L_OFFSET          0x0078U /* GPIO3D Driver Strength Control Low bits */
#define RK_VCCIO3_5_IOC_GPIO3D_DS_L_OFFSET          0x007CU /* GPIO3D Driver Strength Control high bits */
#define RK_VCCIO3_5_IOC_GPIO4C_DS_L_OFFSET          0x0090U /* GPIO4C Driver Strength Control Low bits */
#define RK_VCCIO3_5_IOC_GPIO4C_DS_L_OFFSET          0x0094U /* GPIO4C Driver Strength Control high bits */
#define RK_VCCIO3_5_IOC_GPIO2A_P_OFFSET             0x0120U /* GPIO2A Pull-up/down Control */
#define RK_VCCIO3_5_IOC_GPIO2B_P_OFFSET             0x0124U /* GPIO2B Pull-up/down Control */
#define RK_VCCIO3_5_IOC_GPIO2C_P_OFFSET             0x0128U /* GPIO2C Pull-up/down Control */
#define RK_VCCIO3_5_IOC_GPIO3A_P_OFFSET             0x0130U /* GPIO3A Pull-up/down Control */
#define RK_VCCIO3_5_IOC_GPIO3B_P_OFFSET             0x0134U /* GPIO3B Pull-up/down Control */
#define RK_VCCIO3_5_IOC_GPIO3C_P_OFFSET             0x0138U /* GPIO3C Pull-up/down Control */
#define RK_VCCIO3_5_IOC_GPIO3D_P_OFFSET             0x013CU /* GPIO3D Pull-up/down Control */
#define RK_VCCIO3_5_IOC_GPIO4C_P_OFFSET             0x0148U /* GPIO4C Pull-up/down Control */
#define RK_VCCIO3_5_IOC_GPIO2A_IE_OFFSET            0x0190U /* GPIO2A Input Enable Control */
#define RK_VCCIO3_5_IOC_GPIO2B_IE_OFFSET            0x0194U /* GPIO2B Input Enable Control */
#define RK_VCCIO3_5_IOC_GPIO2C_IE_OFFSET            0x0198U /* GPIO2C Input Enable Control */
#define RK_VCCIO3_5_IOC_GPIO3A_IE_OFFSET            0x01A0U /* GPIO3A Input Enable Control */
#define RK_VCCIO3_5_IOC_GPIO3B_IE_OFFSET            0x01A4U /* GPIO3B Input Enable Control */
#define RK_VCCIO3_5_IOC_GPIO3C_IE_OFFSET            0x01A8U /* GPIO3C Input Enable Control */
#define RK_VCCIO3_5_IOC_GPIO3D_IE_OFFSET            0x01ACU /* GPIO3D Input Enable Control */
#define RK_VCCIO3_5_IOC_GPIO4C_IE_OFFSET            0x01B8U /* GPIO4C Input Enable Control */
#define RK_VCCIO3_5_IOC_GPIO2A_SMT_OFFSET           0x0220U /* GPIO2A Schmitt Trigger Control */
#define RK_VCCIO3_5_IOC_GPIO2B_SMT_OFFSET           0x0224U /* GPIO2B Schmitt Trigger Control */
#define RK_VCCIO3_5_IOC_GPIO2C_SMT_OFFSET           0x0228U /* GPIO2C Schmitt Trigger Control */
#define RK_VCCIO3_5_IOC_GPIO3A_SMT_OFFSET           0x0230U /* GPIO3A Schmitt Trigger Control */
#define RK_VCCIO3_5_IOC_GPIO3B_SMT_OFFSET           0x0234U /* GPIO3B Schmitt Trigger Control */
#define RK_VCCIO3_5_IOC_GPIO3C_SMT_OFFSET           0x0238U /* GPIO3C Schmitt Trigger Control */
#define RK_VCCIO3_5_IOC_GPIO3D_SMT_OFFSET           0x023CU /* GPIO3D Schmitt Trigger Control */
#define RK_VCCIO3_5_IOC_GPIO4C_SMT_OFFSET           0x0248U /* GPIO4C Schmitt Trigger Control */
#define RK_VCCIO3_5_IOC_GPIO_PDIS_OFFSET            0x0288U /* Auto Pull-up/down disable Control */

#ifdef __cplusplus
}
#endif

#endif /* RK_VCCIO3_5_IOC_HW_H */